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Below
is a list of analog blocks currently available as analog IP. Our rigorous structured analog design methodology makes it easy to port these blocks into other semiconductor process.
- Analog-to-Digital Converters (ADCs)
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Resolution and Throughput rate |
Process |
Node |
Application |
More Info |
IP Status |
10bit, 40 MSPS Low Power ADC |
TSMC |
90nM |
WiMAX, RF |
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9bit, 400MSPS pipelined ADC |
TSMC |
90nM |
Datacomm |
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7bit, 800 MSPS Low Power ADC |
TSMC |
90nM |
HDD/DVD |
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8bit, 8 channel input, SAR ADC |
TSMC |
90nM |
SoC/DC measurement |
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4bit, 12Giga Sample/sec flash ADC |
JAZZ |
0.18U |
Optical Communication |
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- High Performance I/Os; Differential Current-Mode Logic Library
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Description |
Process |
Node |
Application |
More Info |
IP Status |
SATA/XAUI output driver |
TSMC |
90nM |
GenI, GenII, XAUI |
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800 Mhz JEDEC output buffer |
TSMC |
90nM |
General purpose |
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3.2Ghz 50 Ohm input buffer |
TSMC |
90nM |
LVDS receiver |
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3.2Ghz 50 Ohm output buffer |
TSMC |
90nM |
LVDS driver |
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3.2Ghz 2i/p, 3i/p multiplexers |
TSMC |
90nM |
Low-jitter clock tree |
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- Continuous-Time Filters (Equalization and Anti-aliasing)
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Description |
Process |
Node |
Application |
More Info |
IP Status |
4th order, 20-200Mhz
programmable with auto-cal |
IBM |
0.25u |
Anti-aliasing/Equalization |
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400Mhz fixed cut-off, low THD;
Drives 10bit ADC |
TSMC |
90nM |
Datacomm/Ethernet |
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- High Performance PLLs
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Description |
Process |
Node |
Application |
More Info |
IP Status |
3.2Ghz clocking PLL |
TSMC |
90nM |
SerDes, Clocking |
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| Silicon Proven |
| Design Proven |
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