MobilitySemi has successfully delivered designs using sub-micron CMOS, BiCMOS, and SOI process technologies from leading fabs such as TSMC, UMC, Infineon, IBM, JAZZ, and Silterra. We are aware of different design methodologies and CAD tools our customers use and we have successfully integrated our designs into the customer CAD flow.

Sample of Analog Front Ends and analog ICs/IPs Mobility has delivered to customers:

  • A 14Ghz,four phase, DLL clock generator for time-interleaved SERDES in 28nM HPC+
  • DLL and Clock Tree design/verification for a 56Ghz DAC in 32nM SOI
  • Verification of a 56Ghz Serializer in 32nM SOI
  • Verification of SerDes blocks (PLL,Rx,Tx,Bias) for a 5Ghz SerDes PHY in 65nM CMOS
  • Process migration and redesign/verification of a 5Ghz PLL for a SerDes PHY IP in 28nM CMOS
  • Turn key Test Chip with 1MSPS, 10-bit SAR ADC and mixed-signal PCB testing board
  • Universal Analog Block: A Switched-Capacitor configurable analog block integrated into uC
  • Process migration/smart porting of a 3rd order modulator based delta-sigma ADC
  • HDD read-channel AFE blocks in 0.25u and 65nM CMOS
  • 4-bit, 12GSPS ADC for OC-192 SONET complaint fiber optic receiver with EDC in 0.18u Jazz BiCMOS
  • Less than 1pS jitter clock tree design for 10G Base-T AFE in 90nM TSMC
  • Analog filter for 10G Base-T AFE in 90nM TSMC

Mobility Design Service Capabilities:

  • Turn Key IC design and debug including PCB design and uC embedded design and software development
  • High performance analog IP development and integration for ASIC development
  • Transistor level Analog Front End design for wired, hard-disk, fiber-optic, sensor, and wireless chips
  • High performance block level analog IC design
    • Nyquist-Rate ADCs and DACs
    • Low jitter PLLs, Current Mode Logic libraries, high-speed transmitters
    • Power management: LDOs, Charge Pumps, DC-DC converters
  • Analog centric test chip design prototyping and debug using main stream foundries
  • Custom Analog and digital mask design (layout)
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